The growth in computer applications that require heavy data traffic and the increasing availability of high-speed transmission lines create a need for a data switching system able to manage a huge amount of data at high rates. Such a data switching system controlled by a host processor has a large external memory for storing data. A peripheral component interconnect (PCI) bus may be employed to provide intercommunication between the host processor and the memory.
The address and data signals on the PCI bus are time multiplexed on the same 32 pins (AD0 through AD31). On the one clock cycle, the combined address/data lines carry the address values to move information between the PCI host and the memory. On the next cycle, the same lines switch to carrying the actual data.
To reduce latency when the PCI host reads data from the external memory, it would be desirable to provide a system for prefetching information expected to be read by the PCI host from the memory, prior to its actual reading by the host.